The invention generally relates to controlling the timing of test modes in a multiple processor system.
A circuit typically undergoes a debugging process for purposes of finding errors, or “bugs,” in the operation of the circuit and correcting these bugs. As an example, the circuit may be a microprocessor, and debugging the microprocessor may involve placing the microprocessor in a debug, or test mode to prevent the microprocessor's execution unit(s) from prefetching and decoding instructions. In this manner, when the microprocessor is in this mode, external circuitry may control the execution unit(s) of the microprocessor and examine the various states of registers of the microprocessor. This ability to observe and control the microprocessor's states facilitates the design and evaluation of a system that incorporates the microprocessor.
Some systems may include multiple microprocessors. In such a system, placing one microprocessor in a test mode may not be beneficial because the other microprocessors and other processing elements of the system continue to operate. Therefore, a precise evaluation of the system and/or the particular microprocessor that is in the test mode may be hindered due to the operations of the other microprocessor(s) and other processing elements of the system.
Thus, a multiple processor system presents challenges relating to debugging such a system. Therefore, there is a continuing need for better ways to debug a multiple processor system.